XC4VLX15_08 Datasheet, PDF (16/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 22: Processor Block APU Interface Switching Characteristics
Description
Symbol
Setup and Hold Relative to Clock (CPMDFCMCLOCK)
APU bus control inputs
APU bus data inputs
Clock to Out
T_PPCDCK_DCDCREN
T_PPCCKD_DCDCREN
T_PPCDCK_RESULT
T_PPCCKD_RESULT
APU bus control outputs
APU bus data outputs
T_PPCCKO_APUFCMDEC
T_PPCCKO_RADATA
Speed Grade
-12
-11
-10
0.33
0.36
0.42
0.20
0.20
0.23
0.61
0.67
0.78
0.20
0.20
0.23
1.53
1.75
2.00
1.53
1.75
2.00
RocketIO Switching Characteristics
Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information.
Table 23: Maximum RocketIO Transceiver Performance
RocketIO Transceiver
Description
Speed Grade
-12
-11
6.5
6.5
-10
3.125
Units
ns, Min
ns, Min
ns, Max
ns, Max
Units
Gb/s
Table 24: RocketIO Reference Clock Switching Characteristics
All Speed Grades
Description
Reference Clock frequency range⁽¹⁾
GREFCLK Reference Clock frequency range⁽¹⁾
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak⁽²⁾
Clock recovery frequency acquisition time
Symbol
F_GCLK
F_GREFCLK
F_GTOL
T_RCLK
T_FCLK
T_DCREF
T_GJTT
T_LOCK
Conditions
CLK
CLK
CLK
20% – 80%
20% – 80%
CLK
CLK
Initial lock of the PLL from
startup (programmable)
Min Typ Max
106
644
106
320
–350
+350
400
400
45
55
40
1
Clock recovery phase acquisition time
T_PHASE
Lock to data after PLL has
relocked to the reference clock.
Includes lock to reference time
(programmable)
Spread Spectrum Clocking⁽³⁾
0% to –0.5%
30
33
Notes:
1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.
2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval.
3. Tested with synchronous reference clock.
Units
MHz
MHz
ppm
ps
ps
%
ps
ms
kHz
T_RCLK
80%
20%
T_FCLK
DS302_04_031708
Figure 3: Reference Clock Timing Parameters
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
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