XC4VLX15_08 Datasheet, PDF (47/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 58: Global Clock Setup and Hold for LVCMOS25 Standard, without DCM
Symbol
Description
Device
Speed Grade
-12
-11
-10
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSFD / T_PHFD
Full Delay
Global Clock and IFF⁽²⁾ without DCM
XC4VLX15
1.82
0.11
2.33
0.19
2.74
0.39
ns
XC4VLX25
1.79
0.20
2.30
0.29
2.70
0.50
ns
XC4VLX40
2.06
0.13
2.61
0.22
3.06
0.44
ns
XC4VLX60
2.39
0.04
2.99
0.12
3.50
0.34
ns
XC4VLX80
2.36
0.16
2.96
0.26
3.47
0.49
ns
XC4VLX100
4.85
–0.09
5.83
–0.09
6.76
–0.01
ns
XC4VLX160
2.56
0.46
3.21
0.59
3.76
0.88
ns
XC4VLX200
N/A
3.57
0.64
4.17
0.95
ns
XC4VSX25
2.12
0.14
2.68
0.23
3.14
0.44
ns
XC4VSX35
2.10
0.21
2.66
0.30
3.12
0.52
ns
XC4VSX55
1.99
0.57
2.53
0.71
2.97
0.98
ns
XC4VFX12
1.82
0.12
2.33
0.20
2.73
0.39
ns
XC4VFX20
1.75
0.38
2.26
0.49
2.65
0.73
ns
XC4VFX40
1.82
0.64
2.34
0.78
2.75
1.05
ns
XC4VFX60
2.42
0.25
3.03
0.35
3.54
0.59
ns
XC4VFX100
1.99
1.11
2.21
1.31
2.60
1.64
ns
XC4VFX140
N/A
2.80
1.26
3.28
1.61
ns
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the
Global Clock input signal with the slowest route and heaviest load.
2. IFF = Input Flip-Flop or Latch.
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
47