XC4VLX15_08 Datasheet, PDF (37/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 44: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
Description
-12
-11
-10 Units
T_{BCCCK_CE} / T_{BCCKC_CE(1)}
CE pins Setup/Hold
0.27
0.00
0.31
0.00
0.35
0.00
ns
T_{BCCCK_S} / T_{BCCKC_S(1)}
S pins Setup/Hold
0.27
0.00
0.31
0.00
0.35
0.00
ns
T_{BCCKO_O}
Maximum Frequency
BUFGCTRL delay
0.70
0.77
0.90
ns
F_MAX
Global clock tree
500
450
400
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters
do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only
needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
DCM and PMCD Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Description
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MS_MIN
CLKOUT_FREQ_1X_LF_MS_MAX
CLK0, CLK90, CLK180, CLK270
CLKOUT_FREQ_2X_LF_MS_MIN
CLKOUT_FREQ_2X_LF_MS_MAX
CLK2X, CLK2X180
CLKOUT_FREQ_DV_LF_MS_MIN
CLKOUT_FREQ_DV_LF_MS_MAX
CLKDV
CLKOUT_FREQ_FX_LF_MS_MIN
CLKOUT_FREQ_FX_LF_MS_MAX
CLKFX, CLKFX180
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MS_MIN
CLKIN_FREQ_DLL_LF_MS_MAX
CLKIN (using DLL outputs)^(1,3,4,5,6)
CLKIN_FREQ_FX_LF_MS_MIN
CLKIN_FREQ_FX_LF_MS_MAX
CLKIN (using DFS outputs only)^(2,3,4)
PSCLK_FREQ_LF_MS_MIN
PSCLK_FREQ_LF_MS_MAX
PSCLK
Outputs Clocks (High Frequency Mode)
CLKOUT_FREQ_1X_HF_MS_MIN
CLKOUT_FREQ_1X_HF_MS_MAX
CLK0, CLK90, CLK180, CLK270
CLKOUT_FREQ_2X_HF_MS_MIN
CLKOUT_FREQ_2X_HF_MS_MAX
CLK2X, CLK2X180
CLKOUT_FREQ_DV_HF_MS_MIN
CLKOUT_FREQ_DV_HF_MS_MAX
CLKDV
Speed Grade
-12
-11
-10
32
32
32
150
150
150
64
64
64
300
300
300
2
2
2
100
100
100
32
32
32
210
210
210
32
32
32
150
150
150
1
1
1
210
210
210
1
1
1
500
450
400
150
150
150
500
450
400
300
300
300
500
450
400
9.4
9.4
9.4
333
300
267
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
37