X5114 Datasheet, PDF (7/40 Pages) Xicor Inc. – System Controller

X5114
NOP
No Operation
NOP is a special instruction opcode which accesses the
device without any operation. It is primarily used in
conjunction with the CSC output. After a NOP, CSC goes
LOW and the device goes into standby, ignoring any
subsequent data sent on the SI pin and putting the SO
pin in a high impedance state. With the NOP instruction,
the host processor can communicate with other SPI
devices (including other X5114s) in the system without
affecting the currently selected device. In this way, an
unlimited number of X5114s can reside in a system.
Memory Access Operations
To decode all 512 bytes in the memory array requires a
9-bit address. This would normally require a 2-byte
memory address. However, the X5114 uses two different
read opcodes (RMH and RML) and two different write
opcodes (WMH and WML) to reduce the number of
bytes in the command, with the most significant bit of the
address incorporated in the instruction opcode. The
RMH and WMH Opcodes access the upper half
($100h-$1FFh) of the array while the RML and WML
Opcodes access the lower half ($000h-$0FFh).
RML
Read Memory Low
The Read Memory Low instruction reads the data in the
lower half of the memory array, from address $000h to
$0FFh. After sending the instruction opcode and byte
address, the data at the selected address shifts out on
the SO line. Continued clocking sequentially shifts out
data stored in memory at the next address and
automatically increments the address to the next location
after each byte of data. When reaching the lower half
Figure 2. NOP (No Operation)
CSa/CSb
SIa/SIb
Device
Address
Instruction
Opcode
SOa/SOb
SR
Data
array boundary ($0FFh), the address counter continues
to the first address in the upper half of the memory
($100h). When reaching the upper address boundary
($1FFh), the address counter rolls over to address
$000h, allowing the read cycle to be continued
indefinitely. The read cycle is terminated by taking CSa or
CSb high.
RMH
Read Memory High
The Read Memory High instruction allows users to read
the data in the upper half of the memory array from
$100h to $1FFh. Its function is similar to the RML
Command.
WML
NONVOLATILE
Write Memory Low
The Write Memory Low instruction writes new data to the
lower half of the memory array from $000h to $0FFh.
Prior to any attempt to write data into the memory array,
the Write Enable Latch must first be set by issuing the
SWEL instruction. The user may write up to 32 bytes of
data to the memory in a single write instruction. The only
restriction is that the 32-byte data must reside on the
same page, i.e. the upper 3 address bits must be the
same for all of the bytes of data to be written. The lowest
5 address bits automatically increment after transmission
of each byte. After the lowest 5 address bits reach
$11111b, they roll over to $00000b while the 3 higher
order address bits remain unchanged. The 32-byte page
can be written with data and then over-written indefinitely.
In this case, only the last 32 bytes of data transmitted will
be written to the EEPROM during the nonvolatile write
cycle which follows.
CSO
CSC
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