X5114 Datasheet, PDF (6/40 Pages) Xicor Inc. – System Controller

X5114
Table 1. Instruction Opcodes
Command Operation
Opcode ⁽³⁾
Operation
HV Write Cycle Bytes⁽²⁾
NOP
00h [0000 0000] No Operation
2+
RML
05h [0000 0101] Read Memory Low
4+
RMH
WML
WMH
SWEL
RWEL
Memory
Access
06h [0000 0110]
09h [0000 1001]
0Ah [0000 1010]
03h [0000 0011]
0Ch [0000 1100]
Read Memory High
Write Memory Low
Write Memory High
Set Write Enable Latch
Reset Write Enable Latch
4+
Y
4+
Y
4+
2
2
RMPR
DFh [1101 1111] Read Multiple Port Registers
16
RPAL
51h [0101 0001] Read Port A Latch
3
RPBL
91h [1001 0001] Read Port B Latch
3
RDVRA
Read Port 52h [0101 0010] Read Desired Value Register Port A
3
RDVRB
92h [1001 0010] Read Desired Value Register Port B
3
RDDRA
54h [0101 0100] Read Data Direction Register Port A
3
RDDRB
94h [1001 0100] Read Data Direction Register Port B
3
WMPR
EFh [1110 1111] Write Multiple Port Registers
Y
11
WDVRA
62h [0110 0010] Write Desired Value Register Port A
Y ⁽¹⁾
3
WDVRB Write Port A2h [1010 0010] Write Desired Value Register Port B
Y⁽¹⁾
3
WDDRA
64h [0110 0100] Write Data Direction Register Port A
Y
3
WDDRB
A4h [1010 0100] Write Data Direction Register Port B
Y
3
RIAE
Read
5Ch [0101 1100] Read IRQA Error Register
3
RIBE
Error
9Ch [1001 1100] Read IRQB Error Register
3
RFCR
Condition
DEh [1101 1110] Read IRQ Failed Command Register
3
RIAM
58h [0101 1000] Read IRQ Mask Register Port A
3
RIBM
Read
98h [1001 1000] Read IRQ Mask Register Port B
3
RICR
Configura- D3h [1101 0011] Read IRQ Configuration Register
3
RPCR
tion
D5h [1101 0101] Read Port I/O Configuration Register
3
RTBL
D0h [1101 0000] Read Threshold/Block Lock Register
3
WIAM
68h [0110 1000] Write IRQ Mask Register Port A
Y
3
WIBM
Write
A8h [1010 1000] Write IRQ Mask Register Port B
Y
3
WICR
Configura- E3h [1110 0011] Write IRQ Configuration Register
Y
3
WPCR
tion
E5h [1110 0101] Write Port I/O Configuration Register
Y
3
WTBL
E0h [1110 0000] Write Threshold/Block Lock Register
Y
3
Notes:
(1) In this condition, the HV Write Cycle will not proceed when the X5114 is configured in the handshake mode.
(2) The number of command bytes listed here is for software addressing mode. For memory sequential read and page write, the
minimum number is 4. The minimum number of bytes required for NOP is 2.
(3) All other possible instruction opcodes are illegal commands.
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