X5114 Datasheet, PDF (11/40 Pages) Xicor Inc. – System Controller

X5114
Table 3. Multiple Register Write Order (WMPR)
Write
Order
1
2
3
4
5
6
7
8
9
Register
DVRA
DVRB
DDRA
DDRB
IAM
IBM
PCR
CR
ICR
Description
Desired Value Reg. A
Desired Value Reg. B
Data Direction Reg. A
Data Direction Reg. B
IRQ Mask Register A
IRQ Mask Register B
Port I/O Configuration Register
Configuration Register
IRQ Configuration Register
WDVRA, WDVRB
NONVOLATILE
Write Desired Value Register A, B
The WDVRA and WDVRB instructions write data to the
Desired Value Registers. See Figure 9 on page 10.
In the general I/O mode, these instructions load the
Desired Value Registers with desired data to monitor the
input/output pin level (Fault Monitoring). This data value
compares with the signal on the corresponding input port
pins. Any differences can generate an interrupt. Taking
CSa or CSb HIGH following the WDVRA or WDVRB
instruction starts a nonvolatile write cycle that mirrors the
data into a nonvolatile location. Power cycling the device
restores the nonvolatile value to the DVRA and DVRB
registers.
In the handshake mode, the WDVRA instruction writes
data directly to the Port A output pins (i.e., no nonvolatile
write cycle) and triggers an output handshake sequence.
The WDVRB instruction writes data directly to the Port B
output pins 3-0 (pins 7-4 are not available since they are
part of the handshake mechanism). Data on Port B pins
3-0 are mirrored into a nonvolatile location by a
nonvolatile write cycle.
WDDRA, WDDRB
NONVOLATILE
Write Data Direction Register A, B
The WDDRA and WDDRB instructions write new data to
the Data Direction Registers. See Figure 9 on page 10.
This selects the direction of each of the port pins.
Read Error Conditions
RIAE, RIBE
Read IRQA, IRQB Error Register
The RIAE and RIBE instructions return the contents of
the IRQ Error Registers. See Figure 8 on page 10. This
provides status on port error conditions.
RFCR
Read Failed Command Register
The Read Failed Command Register instruction allows
the host to track the most recent bad command. A bad
command is defined as one with:
• an unknown or illegal instruction opcode
• an incomplete transmission of a command which can
be instruction opcode, address, or data. As an exam-
ple, CSa or CSb goes HIGH when the clock count is
not a multiple of 8.
Detection of a bad command sets a Failed Command
(FC) flag in the Status Register (SR) and asserts the
IRQA or IRQB signal, if enabled. The Failed Command
Register contains the Error information. The host read of
the Failed Command Register clears IRQA and IRQB
signals and the FC flag. However, the RFCR instruction
will not clear the Failed Command Register.
The FCR will only store the most recent bad command if
there were more than one bad command in a sequence.
Also the information in the FCR is only updated when a
bad command is discovered.
Read Configuration
RIAM, RIBM
Read IRQA, IRQB Mask Register
The RIAM and RIBM instructions return the contents of
the respective IRQ Mask Register. See Figure 8 on page
10.
RICR
Read IRQ Configuration Register
The RICR instruction returns the contents of the IRQ
Configuration Register. See Figure 8 on page 10.
RPCR
Read Port I/O Configuration Register
The RPCR instruction returns the contents of the PORT
I/O Configuration Register. See Figure 8 on page 10.
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