X5114 Datasheet, PDF (12/40 Pages) Xicor Inc. – System Controller

X5114
RTBL
Read Threshold/Block Lock Register
The RTBL instruction returns the contents of the
Threshold/Block Lock Register. See Figure 8 on page 10.
Write Configuration
WIAM, WIBM
NONVOLATILE
Write IRQA, IRQB Mask Register
The WIAM and WIBM instructions write new data to the
respective IRQ Mask Register. See Figure 9 on page 10.
WICR
NONVOLATILE
Write IRQ Configuration Register
The WICR instruction writes new data into the IRQ
Configuration Register to change interrupt operations.
See Figure 9 on page 10.
WPCR
NONVOLATILE
Write Port I/O Configuration Register
The WPCR instruction writes new data into the Port I/O
Configuration Register to change the Port I/O
functionality. See Figure 9 on page 10.
WTBL
NONVOLATILE
Write Threshold/Block Lock Register
The WTBL instruction writes new data to the
Threshold/Block Lock Register to select different modes
of operations. See Figure 9 on page 10.
CONTROL/STATUS REGISTERS
The X5114 has a number of registers to monitor and
control the operation of the device. Access to the control
registers are via SPI Commands.
The status register contains the status of the most critical
operating conditions. The contents are placed on the
output pins in synchronization with the incoming op code
(providing the device is addressed correctly). The status
register cannot be written to directly.
Status Register (SR)
WIP WEL PCE FC RDR XRE IRQA IRQB
Volatile
MSB
LSB
WIP Write In Progress flag.
0 no nonvolatile write cycle in progress
1 nonvolatile write cycle is in progress
WEL Write Enable Latch flag
0 write enable latch has not been set
1 write enable latch is set
PCE PCE Pin Input Status
0 PCE pin is at Logic 0
1 PCE pin is at Logic 1
FC Failed Command flag—Power on
default = 1
0 no command failures
1 command failure (abnormal termination)
RDR Receive Data Ready flag
(Single Read Input and Bidirectional Modes)
0 no data is latched
1 latched data is ready for read at Port A
XRE Transmit Register Empty flag
(Output and Bidirectional Modes)
Port A data has not been read by the external
0 system and is not ready to accept new data
from the SPI interface
1
Port A is ready to accept the new data from the
SPI interface.
IRQA Interrupt Port A
0 Interrupt A is not asserted
1 Interrupt A is asserted
IRQB Interrupt Port B
0 Interrupt B is not asserted
1 Interrupt B is asserted
12