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X5114 Datasheet, PDF (1/40 Pages) Xicor Inc. – System Controller
X5114
System Controller
FEATURES
• Simplifies Backplane Communications
• Monitor Fault and “Hot Docking” Conditions
• Ten Level Selectable Input Threshold
• Two Fully Redundant SPI Serial I/O Ports
• Programmable Output or Input Port Pins
—16 General I/O pins
—8 bit Port with 4 Handshake Modes
• Single Read Input Mode
• Multiple Read Input Mode
• Output Mode
• Bidirectional Mode
—Port Tristate Control
• Programmable Interrupt and Mask Options
• 8-bit Direct Address Decoder allows Cascaded
255+ devices on one SPI bus
• 4K bits of EEPROM with 32 byte page write
• Default Output Data on Port at Power-up
• High Reliability EEPROM
—Endurance - 105 Data Changes
—Data Retention - 100 years
• 44-Pin PLCC, 48-Lead TQFP
FUNCTIONAL DIAGRAM
DESCRIPTION
The X5114 is a single-chip system controller that is used
in applications such as multiprocessing, telecommunica-
tions, data communications, cable systems, set top
boxes, etc. The chip can implement features such as
backplane communication, hot docking, cable diagnos-
tics, etc.
The X5114 makes extensive use of nonvolatile memory
with 4,096 bits of general purpose EEPROM, nonvolatile
configuration registers, and nonvolatile programming of
the port pins. The ports can be set up as sixteen general
I/Os with pin selectable data direction (including eight
inputs with nonvolatile threshold selections) or as an
eight bit port with handshake. The chip is controlled via
two redundant 2MHz SPI serial ports.
A sophisticated interrupt controller provides notification of
a failed SPI command, changing conditions on an input,
handshake status, and I/O errors. Interrupts are
maskable.
On-chip EEPROM provides nonvolatile storage of
system status, manufacturing information, board ID or
other parameters.
CSO
CSC
CSa
SIa
SOa
SCKa
CSb
SIb
SOb
SCKb
A0
.
.
.
.
A7
SPI_A
SPI_B
Address
Select
Decode
= EEPROM
©Xicor, Inc. 1994 - 1997 Patents Pending
7054-1.2 10/29/00 T13/C8/D24 SH
Serial
Engine/
Data Flow
Controller
256 X 8
Port
Config
Regs
256 X 8
EEPROM
1
Port A Each Pin
PA7
Desired
PA6
Value
Output
PA5
PA4
PA3
Port A
PA2
Input
PA1
Latch
PA0
Interrupt
Logic
Threshold
Adjust
Interrupt
Control A/B
IRQA
IRQB
PCE
Interrupt
Logic
Handshake
Logic
(PB7-PB4)
Desired
Value
Port B
Latch
Output
Port A
Handshake
Input
Port B Each Pin
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Characteristics subject to change without notice