X5114 Datasheet, PDF (22/40 Pages) Xicor Inc. – System Controller

X5114
Figure 19. Bi-directional Mode - Parallel Write
PEN (PB4 in)
R/W (PB 7 in)
Port A Data
RDR (Flag)
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
Figure 20. Bi-directional Mode - SPI Read
CSa/CSb
SCKa/SCKb
SIa/SIb
SOa/SOb
Device Address
RPAL Instruction
DD D DD D D DO OO OO O O O
AA AAA A A A P PP PP P P P
76 543 2 1 07 65 43 2 1 0
Don’t Care
Status Register Data
PAL Data Out
S S S S S S S S DDDDDDD D
7 6 5 4 3 21 0 7654321 0
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
RDR (Flag)
• PLS bit - The pulse bit (PLS) HIGH sets RDRF signal
to operate in an “interlocked” mode, where RDRF
“tracks” the XRE flag. The PLS bit HIGH sets RDRF to
operate in a “pulsed” mode.
• The TRI bit HIGH disables the tri-state operation of the
port, making the outputs always active in this mode.
Fault monitoring on pins PA7-PA0, PB7 and PB6 is
disabled in this mode. Fault monitoring and general I/O
functionality of the remaining six Port B pins remains
user configurable.
Bi-directional Mode
EXAMPLE APPLICATION:
This Mode provides full handshake capability to allow
bidirectional interraction between the host, communicating
over the SPI port and a slave processor communicating
over parallel port A. In this mode, Port A looks like an
SRAM to the slave processor.
MODE ENTRY:
Set HS2, HS1, HS0 bits in PCR register to 111.
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