X5114 Datasheet, PDF (5/40 Pages) Xicor Inc. – System Controller

X5114
Hardware Device Addressing Mode
In this addressing mode, all the external address pins are
tied to logic “0”. The device is selected solely by the CSa
or CSb pins. As soon as the CSa or CSb pin goes LOW
and stays LOW, the device will be in the active state. No
slave address byte is needed in this mode.
Chip Select Output/Device Cascade (CSO/CSC)
The CSO and CSC output pins have two major functions.
The CSO pin can be used as a chip select indicator. This
signal indicates that the host processor has selected this
device.
The CSC signal allows the cascade of multiple banks of
X5114 devices. In a cascade mode, the CSC output of a
selected X5114 selects another external device by using
the NOP instruction. (see "NOP" on page 7 )
Instruction Opcode
The second byte transmitted to the device (or the first
byte in hardware addressing mode) contains the
Instruction opcode that defines the operation to be
performed. All the opcode bits have been specially
arranged to achieve a 2-bit difference between opcodes
to reduce the possibility of inadvertent operations.
Instruction Opcode
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
MSB
LSB
OP7, OP6
“00” = memory operation,
“01” = port A operation,
“10” = port B operation,
“11” = Control Register operation.
OP5, OP4
“01” = port-related read command,
“10” = port-related write command.
OP3, OP2, OP1, OP0
“0000” = Configuration Register operation,
“0001” = Port Latch operation,
“0010” = Port Desired Value Register operation,
“0100” = Port Data Direction Register operation,
“1000” = Port IRQ Mask Register operation,
“0011” = Port IRQ Configuration Register operation,
“0101” = Port I/O Configuration Register operation,
“1100” = Port IRQ Error Register operation,
“1110” = Port IRQ Failed Command Register operation,
“1111” = Port Registers operation.
INSTRUCTION SUMMARY
Each instruction must be proceeded with a HIGH to LOW
transition on CSa or CSb and be terminated by a LOW to
HIGH transition on CSa or CSb. There is no restriction as
to which of the two SPI interface ports receives an
instruction or combination of instructions.
If the instruction initiates a nonvolatile write operation, as
indicated in Table 1, “Instruction Opcodes,” on page 6
and in the instruction definitions, the write cycle begins at
the rising edge of the CSa or CSb signals. However if the
CSa or CSb goes HIGH before the device address,
command, and data are sent completely (e.g. when the
clock is not a multiple of eight), then no nonvolatile write
cycle starts, the WEL will not reset, and there will be an
incomplete transmission (i.e. a failed command). In a
failed command, an interrupt signal informs the host
processor of a fault condition. After completion of a
nonvolatile write cycle, the circuitry automatically clears
the Write Enable Latch (WEL).
The nonvolatile write typically takes much less than the
maximum time to complete. However, the Status
Register WIP bit indicates the nonvolatile wrte status.
After receiving a valid address, the X5114 returns the
status register contents so an host has an early end of
write cycle indication. If WIP is HIGH, the write is still in
progress. If WIP is LOW, the X5114 is available for
continued operations.
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