X5114 Datasheet, PDF (4/40 Pages) Xicor Inc. – System Controller

X5114
The master will always initiate data transfers and provide
the clock for both transmit and receive operations. The
X5114 is considered a slave for all operations.
The X5114 has special addressing mechanisms to allow
up to 255 devices (or more after using the NOP
command) to reside on one SPI communication bus.
This reduces the number of bus lines required to talk to
multiple X5114 devices.
Communication to the device begins with a start
condition. This consists of the falling edge of CSa or CSb.
Following a CSa/CSb HIGH to LOW, the master selects
one of many X5114 devices on the SPI bus, by
transmitting a slave address (Software Device
Addressing) or selects the only device on the bus using
the CSa/CSb signal (Hardware Device Addressing).
Software Device Addressing Mode
In this device addressing mode, each X5114 has a
unique slave address externally specified by the A7-A0
pins. The first byte transmitted to the device contains the
device address. This address is compared with the
external address pins, A7-A0. If matched, the device
performs the task specified by the Instruction opcode
sent in the next byte. If there is no match, the X5114
returns to the standby state.
Device Address (Software Addressing only)
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
MSB
LSB
FIGURE 1. SPI Communications - Addressing Modes (Read example)
Software Addressed:
CSa/CSb
SCKa/SCKb
SIa/SIb
SOa/SOb
Device Address
Instruction
D D D DD D D D O OO OO O O O
AA AAA A AA P PP PP P P P
76 543 2 10 7 65 43 2 1 0
Data In
Don’t Care
Status
Data Out
S S S S S S S S DDDDDDD D
7 6 5 4 3 21 0 7654321 0
CSO
Hardware Addressed:
CSa/CSb
SCKa/SCKb
SIa/SIb
SOa/SOb
CSO
Instruction
OO OOOOOO
PP PPPPPP
76 543210
Data In
Don’t Care
Status
Data Out
S S S S S S S S D DDDDDD D
7 6 5 4 3 2 1 0 7 654321 0
4