X9470 Datasheet, PDF (19/25 Pages) Xicor Inc. – RF Power Amplifier (PA) Bias Controller

Preliminary Information
X9470
X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION
Table 2. Status Register (SR)
Byte
Addr
SR7
SR6
SR5
SR4
SR3
SR2
0F hex
SHDN
INC/DEC
0
CS
0
0
SR1
WEL
SR0
Gain
STATUS REGISTER (SR)
The Status Register is located at address 0F<hex>.
This is a register used to control the write enable
latches, and monitor status of the SHDN, INC/DEC,
and CS pin. This register is separate from the Control
Register.
SR7: SHDN: Vbias SHDN Flag. Read Only—Volatile.
The bit keeps status of the shutdown pin, SHDN. When
this bit is HIGH, the SHDN pin is active and the V_BIAS
output is disabled. When this bit is LOW, the SHDN pin
is low and V_BIAS output is enabled.
SR6: INC/DEC : Read Only—Volatile. This bit keeps
status of the INC/DEC pin. When this bit is HIGH the
counter is in increment mode, when this bit is LOW the
counter is in decrement mode.
SR4: CS: Read Only—Volatile. This bit keeps status
on the CS pin. When this bit is HIGH, the X9470 is in
closed loop mode (Rbias adjustment enabled). When
this bit is LOW the x9470 is in open loop mode (no
Rbias adjustments).
SR2, SR3, SR5: Read only
For internal test usage, should be set to 0 during SR
writes.
SR1: WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the registers during
a write operation. This bit is a volatile latch that powers
up in the LOW (disabled) state. While the WEL bit is
set LOW, Nonvolatile writes to the registers will be
ignored, and all writes to registers will be volatile. The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once
this write operation is completed and a STOP com-
mand is issued, nonvolatile writes will then occur for all
NOVRAM registers and control bits. Once set, the,
WEL bit remains set until either reset to 0 (by writing a
“0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again.
SR0: Gain - NOVRAM
Selects V_OUT and IA gain. When SR0=0, V_OUT gain=20x,
IA gain=50x. When SR0=1, V_OUT gain=50x, and IA
gain=20x. Default setting is 0.
CONTROL REGISTERS (CR)
The control registers are organized for byte operations.
Each byte has a unique byte address as shown in
Table 3 below.
Table 3. Control Registers (CR)
Byte
Addr.
Reg
<HEX> Description Name 7
6
5
00 hex DCP for Vbias Vbias Vb7 Vb6 Vb5
01 hex
DCP for
VREF
Vref
X
X Vr5
Note: 02H to 0EH are reserved for internal manufacturing use.
Bit
4
3
2
1
0 Memory Type
Vb4 Vb3 Vb2 Vb1 Vb0
NOVRAM
Vr4 Vr3 Vr2 Vr1 Vr0
NOVRAM
REV 11.16 3/20/03
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