W921E840A Datasheet, PDF (9/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
4. PIN DESCRIPTION
SYMBOL
I/O
FUNCTION
OSCI
I
Main oscillator input pin with internal capacitor
OSCO
P2.0 to P2.3
O
Main oscillator output pin
I/O^V I/O port 2 with large sink current
P3.0/ANI0 to
P3.3/ANI3
P4.0
P4.1
P4.2
P4.3/INT0
I/O I/O port 3 or analog input (ANI0 to ANI3) pins
I/O^K I/O pin P4.0 or the input pin of interrupt port
I/O^K I/O pin P4.1 or the input pin of interrupt port
I/O^K I/O pin P4.2 or the input pin of interrupt port
I/O^K I/O pin P4.3 or INT0 input pin
P5.0/TM1
I/O I/O pin P5.0 or the controlled pin of timer 1
P5.1/TM2
I/O I/O pin P5.1 or the controlled pin of timer 2
P5.2/VREF
I/O
I/O pin P5.2 or the VREF input pin of the comparator
P5.3/DAOUT
P6.0/WDATA
P6.1/WCLK
I/O I/O pin P5.3 or the output pin of 8-bit D/A converter
I/O^K I/O pin P6.0 or the data output pin of serial interface
I/O^K I/O pin P6.1 or the clock I/O pin of WDATA
P6.2/RDATA
P6.3/RCLK
PA.0 to PA.3
PB.0 to PB.3
PC.0 to PC.3
PD.0 or XT
PD.1 or XT
I/OK I/O pin P6.2 or the data input pin of serial interface
I/O^K I/O pin P6.3 or the clock I/O pin of RDATA
I/O^K I/O port A with wake up stop mode function
I/O^K I/O port B with wake up stop mode function
I/O^K I/O port C. PC.3 can be as 32.768 KHz output buffer
I/O^{K I/O pin PD.0 or 32.768 KHz subsystem clock output pin (with}
internal capacitor)
I/O^K I/O pin PD.1 or 32.768 KHz subsystem clock input pin
DTMF
O
Dual tone multi-frequency output pin
BTG
O
Beep tone generator output pin
RESET
I
Reset input pin with low active
VDD
I
Positive power supply input pin
VSS
I
Negative power supply input pin
Notes:
V open drain option by software
K open drain and pull high resistor option by software
Publication Release Date: July 1999
-9-
Revision A3