W921E840A Datasheet, PDF (36/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
INTCT2 register: (address = 03AH, default data = 0H)
b3
b2
b1
b0
Reserved
0: INT0 pin interrupt disable
1: INT0 pin interrupt enable
0: Serial port interrupt disable
1: Serial port interrupt enable
0: Comparator interrupt disable
1: Comparator interrupt enable
INTCT3 register: (address = 03BH, default data = 0H)
b3
b2
b1
b0
Reserved
0: Pin P4.0 interrupt disable
1: Pin P4.0 interrupt enable
0: Pin P4.1 interrupt disable
1: Pin P4.1 interrupt enable
0: Pin P4.2 interrupt disable
1: Pin P4.2 interrupt enable
6.12.2 Interrupt Enable Flag
When the interrupt is enabled by the event, the program counter will jump to the interrupt address and
the enable interrupt flag (ENINT) bit0 is cleared, at the same time, all the interrupt will be disabled.
The only way to enable the interrupt again is to set the ENINT bit0 or execute the RTNI instruction.
ENINT register: (address = 034H, default data = 0H)
b3
b2
b1
b0
Reserved ^{Reserved Reserved}
0: Disable all interrupt
1: Enable all interrupt
When the interrupt is enabled by the event, the individual interrupt request signal is cleared by the
hardware automatically, but the other interrupt request signals will remain the same condition. The
only method of resetting the interrupt request signal is to execute the instruction CLR EVF, #I (I is a
8bits data, for example, CLR EVF, #00000001b instruction implies to clear TM0 interrupt request
signal), it is a 2 words / 2 cycles instruction; the format of the immediate data is shown below.
i7 i6 i5 i4 i3 i2 i1 i0
1: TM0 interrupt request signal is cleared
1: TM1 interrupt request signal is cleared
1: TM2 interrupt request signal is cleared
1: TM3 interrupt request signal is cleared
1: INT0 pin interrupt request signal is cleared
1: Serial port interrupt request signal is cleared
1: Comparator interrupt request signal is cleared
1: P4.0 to P4.2 interrupt request signal is cleared
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