W921E840A Datasheet, PDF (29/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
TM0 will underflow when TM0 set register is from 00H to 0FFH and the value in the TM0MSB and
TM0LSB will be auto reloaded to the TM0 set register when the STTM0 bit2 is set. TM0 will decrease
by 1 at the frequency of timer 0 clock after timer 0 has started.
If at any time the STTM0 bit3 is from 0 to 1 (disable to enable) in the timer mode, the TM0MSB and
TM0LSB will be auto reloaded to the TM0 set register again and restart the timer 0. TM0 will stop
operating while the STTM0 bit3 is reset to 0.
The format of the TM0 low speed register (TM0LSR) is described below:
TM0LSR register: (address = 024H, default data = 0H, only for W921E841A, 843A, 844A)
b3
b2
b1
b0
Reserved
Reserved
b1 b0 Input frequency (fsys1)
00
fsub/2 Hz
01
fsub/8 Hz
10
fsub/16 Hz
11
fsub/32 Hz
The TM0 starts to down count when the STTM0 register bit3 is set. When TM0 underflows, the
STTM0 bit3 will be reset by hardware to stop TM0 if the auto-reload is disabled, but the STTM0 bit3
will not be reset if the auto-reload is enabled.
When the TM0 normal function is performed, the watch-dog timer function will be disabled
automatically.
The format of the TM0 status register (STTM0) is described below:
STTM0 register: (address = 023H, default data = 0H)
b3
b2
b1
b0
0:TM0 normal function selected
1:Watch-dog timer (WDT) selected
0:WDT not underflow
1:WDT underflow
0:TM0 auto-reload disable
1:TM0 auto-reload enable
0:TM0 stop
1:TM0 start
If TM0 works as the watch-dog timer (WDT), the bit1 of the STTM0 register will be set when the WDT
is underflow, in the meanwhile, the system is reset just as with power on reset except the STTM0 bit1.
The WDT (STTM0 bit1) will be reset to zero only with the power on reset or the RAM write mode.
In the timer mode or event counter mode the time out will be the programming data subtract 1
([TM0MSB, TM0LSB]-1). It is the same in the TM1, TM2 and TM3.
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Publication Release Date: July 1999
Revision A3