W921E840A Datasheet, PDF (39/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
The hold released status flag1, 2, 3 (HRSTS1, 2, 3, address = 03CH, 03DH, 03EH) indicate by which
interrupt source the hold mode has been released, and is loaded by hardware. When any bit of
HRSTS1, 2, 3 is "1," the hold mode will be released and HOLD instruction in invalid. The bit
descriptions are as follows:
HRSTS1 register: (address = 03CH, read only, default data = 0H)
b3
b2
b1
b0
1: Hold was released by TM0
1: Hold was released by TM1
1: Hold was released by TM2
1: Hold was released by TM3
HRSTS2 register: (address = 03DH, read only, default data = 0H)
b3
b2
b1
b0
Reserved
1: Hold was released by the INT0 pin
1: Hold was released by serial port
1: Hold was released by comparator
HRSTS3 register: (address = 03EH, read only, default data = 0H)
b3
b2
b1
b0
Reserved
1: Hold was released by pin P4.0
1: Hold was released by pin P4.1
1: Hold was released by pin P4.2
HRSTS1, 2 and 3 are read only registers and can be reset by the instruction CLR EVF, #I. When EVF
has been reset, the corresponding bit of HRSTSn (n = 1 to 3) is reset simultaneously.
6.13.3 Stop Mode
The µC enters the stop mode only when the STOP instruction is executed. Because the oscillator is
stopped, all functions in this chip are stopped.
The stop mode can be released by the RESET pin, INT0 pin, P4.0 to P4.2, PA port or PB port. The
stop condition release flag (STPRF, address = 035H) is the stop mode release control register.
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Publication Release Date: July 1999
Revision A3