W921E840A Datasheet, PDF (37/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
6.13 Operating Mode
There are three types of operating mode in this chip  normal mode, hold mode and stop mode.
6.13.1 Normal Mode
All functions works well and the µC operates according to the clock generated by the system clock.
6.13.2 Hold Mode
In hold mode, all operations of µC cease, except for the operation of the oscillator, timer/counter,
serial port and interrupt active pins. The µC enters hold mode when the HOLD instruction is executed.
The hold mode can be released only by the RESET pin or the interrupt request signal. Before The
device enters the hold mode, the hold mode release flag1, 2, 3 (HMRF1, 2, 3, address = 036H, 037H,
038H) must be set to define the hold mode release conditions. If interrupt condition is met and
enabled in hold mode, the interrupt will be accepted to release hold mode and jump to interrupt vector
to execute interrupt service routine. For more details, refer to the following flags and flow chart.
HMRF1 register: (address = 036H, default data = 0H)
LSB
MSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
NOP
MOV A, B
MOV A, Mx
MOV A, @M
MOV A, W
MOV A, V
MOV A, U
SRL A
INC B
ADD A, Mx
ADD A, @M
CLRB Mx, bit
1
MOV B, A
MOV B, Mx
MOV B, @M
SRH A
INC DP
ADC A, Mx
ADC A, @M
CLRB @M, bit
2
MOV Mx, A
MOV Mx, B
SLL A
DEC B
SUB A, Mx
SUB A, @M
SETB Mx, bit
3
MOV @M, A
MOV @M, B
4
MOV W, A
SLH A
DEC DP
SBC A, Mx
SBC A, @M
SETB @M, bit
RRC A
ANL A, Mx
ANL A, @M
CLR EVF
XCH A, B
MOV DP, #I
SOP
5
MOV V, A
ORL A, Mx
ORL A, @M
SIP
6
MOV U, A
7
RLC A
XRL A, B
CMP A, B
XRL A, Mx
CMP A, MX
XRL A, @M
CMP A, @M
SET CF
CLR CF
XCH V, CV
XCH U, CU
HOLD
RTN
STOP
RTNI
8
ADD A, #I
9
ADC A, #I
A
SUB A, #I
B
SBC A, #I
C
ANL A, #I
D
ORL A, #I
E
XRL A, #I
F
CMP A, #I
1W/1C
1W/2C
1W/3C
2W/2C
2W/3C
3W/3C
Undecided
HMRF2 register: (address = 037H, default data = 0H)
b3
b2
b1
b0
Reserved
0: INT0 pin hold released disable
1: INT0 pin hold released enable
0: Serial port hold released disable
1: Serial port hold released enable
0: Comparator hold released disable
1: Comparator hold released enable
HMRF3 register: (address = 038H, default data = 0H)
b3
b2
b1
b0
Reserved
0: Pin P4.0 hold released disable
1: Pin P4.0 hold released enable
0: Pin P4.1 hold released disable
1: Pin P4.1 hold released enable
0: Pin P4.2 hold released disable
1: Pin P4.2 hold released enable
- 37 -
Publication Release Date: July 1999
Revision A3