W921E840A Datasheet, PDF (22/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
SRMNR register: (address = 00AH, default data = 0H)
b3
b2
b1
b0
SRLNR register: (address = 009H, default data = 2H)
b3
b2
b1
b0
The default data in SRMNR and SRLNR are 0 and 2, meaning that the default serial interface is used
to transmit/receive 8-bit data serially. As soon as the above two register are programmed and the
instructions such as SOP or SIP are executed, the serial transmitter/receiver multi-nibble function will
be performed. The transmitted/received number will be auto increased by one when each nibble is
transmitted/received until the number is equal to SRLNR, SRMNR registers. Even if the HOLD
instruction is executed, the SOP or SIP function will continue executing until the transmitter/receiver
function has been completed. However, executing the STOP instruction will stop all serial
transmitter/receiver function.
The transceiver data will be latched on the rising or falling edge of the clock; this is determined by the
serial clock inverter control register (SRINV, address = 00CH). Before SOP or SIP instruction is
executed the SRINV register must be set to the exact value. Once the bit3 and bit2 of SRINV register
are both cleared to zero, the serial transceiver function will be reset to initial status immediately.
SRINV register: (address = 00CH, default data = 0H)
b3
b2
b1
b0
0: Serial data latch at SCLK1/SCLK2 rising edge
(normal high)
1: Serial data latch at SCLK1/SCLK2 falling edge
(normal low)
0: SCLK1and SCLK2 pins work as the internal
clock output pin
1: SCLK1and SCLK2 pins work as the external
clock input pin
0: SCLK2 and SDATA2 disable (H-Z)
1: SCLK2 and SDATA2 enable
0: SCLK1 and SDATA1 disable (H-Z)
1: SCLK1 and SDATA1 enable
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