W921E840A Datasheet, PDF (24/58 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E840A/W921C840
Normally the WCLK or RCLK pin will remain in high state and the serial data will be latched at the
rising edge of the WCLK or RCLK signal, but the serial clock inverter control register (SRINV) will
invert the above function. In this case WCLK or RCLK pin will remain in low state and the serial data
will be latched at the falling edge of the WCLK or RCLK signal.
The transmitting serial clock can come from WCLK or RCLK, depending on which one is enable. If
the serial function is disabled, it will cause the relative pins to be high impendance and it will not
affect the contents of serial buffer registers (start at address 050H).
6.7 DTMF Generator
There is one dual tone multi-frequency (DTMF) generator channel in this chip. The correct DTMF
output frequency is decided by the OSCCTR register as shown below:
OSCCTR register: (address = 013H, default data = 0H)
b3
b2
b1
b0
Reserved
b2 b1 b0
000
001
010
011
100
101
Osc. Selection
400 KHz
800 KHz
2 MHz
4 MHz
Reserved
3.58MHz
There are four bits in the DTMF register; the functions are described in the following table:
DTMF register: (address = 014H, default data = 0H)
b3 b2 b1 b0
XX00
XX01
XX10
XX11
00XX
01XX
10XX
11XX
Note: X Ä don't care
Function Description
Column 1 (1209 Hz) output
Column 2 (1336 Hz) output
Column 3 (1477 Hz) output
Column 4 (1633 Hz) output
Row 1 (697 Hz) output
Row 2 (770 Hz) output
Row 3 (852 Hz) output
Row 4 (941 Hz) output
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