English
Language : 

W77IE58 Datasheet, PDF (84/90 Pages) Winbond – 8-BIT MICROCONTROLLER
Preliminary W77IE58
Movx Characteristics Using Strech Memory Cycles, continued
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS STRECH
ALE Low to RD or WR Low
Port 0 Address to RD or WR
Low
tLLWL
tAVWL
0.5 tCLCL - 5
1.5 tCLCL - 5
tCLCL - 5
2.0 tCLCL - 5
0.5 tCLCL + 5
1.5 tCLCL + 5
nS
tMCS = 0
tMCS>0
nS
tMCS = 0
tMCS>0
Port 2 Address to RD or WR
Low
tAVWL2
1.5 tCLCL - 5
2.5 tCLCL - 5
nS
tMCS = 0
tMCS>0
Data Valid to WR Transition
Data Hold after Write
RD Low to Address Float
tQVWX
tWHQX
tRLAZ
-5
1.0 tCLCL - 5
tCLCL - 5
2.0 tCLCL - 5
0.5 tCLCL - 5
nS
tMCS = 0
tMCS>0
nS
tMCS = 0
tMCS>0
nS
RD or WR high to ALE high
tWHLH
0
1.0 tCLCL - 5
10
1.0 tCLCL + 5
nS
tMCS = 0
tMCS>0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS
for each selection of the Stretch value.
M2
M1
M0
MOVX Cycles
tMCS
0
0
0
2 machine cycles
0
0
0
1
3 machine cycles
4 tCLCL
0
1
0
4 machine cycles
8 tCLCL
0
1
1
5 machine cycles
12 tCLCL
1
0
0
6 machine cycles
16 tCLCL
1
0
1
7 machine cycles
20 tCLCL
1
1
0
8 machine cycles
24 tCLCL
1
1
1
9 machine cycles
28 tCLCL
Explanation of Logic Symbols
In order to maintain compatibility with the original 8051 family, this device specifies the same parameter
for each device, using the same symbols. The explanation of the symbols is as follows.
t
Time
A
Address
C
Clock
D
Input Data
H
Logic level high
L
Logic level low
I
Instruction
P
PSEN
Q
Output Data
R
RD signal
V
Valid
W
WR signal
X
No longer a valid state
Z
Tri-state
- 84 -