W77IE58 Datasheet, PDF (52/90 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W77IE58
The W77IE58 can be woken from the Power Down mode by forcing an external interrupt pin activated,
provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and the external
input has been set to a level detect mode. If these conditions are met, then the low level on the external
pin re-starts the oscillator. Then device executes the interrupt service routine for the corresponding
external interrupt. After the interrupt service routine is completed, the program execution returns to the
instruction after the one which put the device into Power Down mode and continues from there. When
RGSL(EXIF.1) bit is set to 1, the CPU will use the internal RC oscillator instead of crystal to exit Power
Down mode. The microcontroller will automatically switch from RC oscillator to crystal after clock is
stable. The RC oscillator runs at approximately 2−4 MHz. Using RC oscillator to exit from Power Down
mode saves the time for waiting crystal start-up. It is useful in the low power system which usually be
awakened from a short operation then returns to Power Down mode.
Table 5. Status of external pins during Idle and Power Down
Mode
Program
ALE
Memory
PSEN
PORT0 PORT1
PORT2 PORT3
Idle
Internal
1
Idle
External
1
Power Down Internal
0
Power Down External
0
1
Data
Data
Data
Data
1
Float
Data
Address
Data
0
Data
Data
Data
Data
0
Float
Data
Data
Data
Reset Conditions
The user has several hardware related options for placing the W77IE58 into reset condition. In general,
most register bits go to their reset value irrespective of the reset condition, but there are a few flags
whose state depends on the source of reset. The user can use these flags to determine the cause of
reset using software. There are two ways of putting the device into reset state. They are External reset
and Watchdog reset.
External Reset
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST pin
must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset circuitry
then synchronously applies the internal reset signal. Thus the reset is a synchronous operation and
requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However
since the other two reset sources have flags, the external reset can be considered as the default reset if
those two flags are cleared.
The software must clear the POR flag after reading it, otherwise it will not be possible to correctly
determine future reset sources. If the power fails, i.e. falls below Vrst, then the devi ce will once again go
into reset state. When the power returns to the proper operating levels, the device will again perform a
power on reset delay and set the POR flag.
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