W77IE58 Datasheet, PDF (57/90 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W77IE58
Execution continues from the vectored address till an RETI instruction is executed. On execution of the
RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what is was after the hardware
LCALL, if the execution is to return to the interrupted program. The processor does not notice anything if
the stack contents are modified and will proceed with execution from the address put back into PC. Note
that a RET instruction would perform exactly the same process as a RETI instruction, but it would not
inform the Interrupt Controller that the interrupt service routine is completed, and would leave the
controller still thinking that the service routine is underway.
Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 to INT5 , they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all three
conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four
machine cycles to be completed. Thus there is a minimum time of five machine cycles between the
interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the W77IE58 is performing a write to IE, IP, EIE or EIP and then
executes a MUL or DIV instruction. From the time an interrupt source is activated, the longest reaction
time is 12 machine cycles. This includes 1 machine cycle to detect the interrupt, 2 machine cycles to
complete the IE, IP, EIE or EIP access, 5 machine cycles to complete the MUL or DIV instruction and 4
machine cycles to complete the hardware LCALL to the interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine cycles
and not more than 12 machine cycles. The maximum latency of 12 machine cycle is 48 clock cycles.
Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96 machine
cycles. This is a 50% reduction in terms of clock periods.
PROGRAMMABLE TIMERS/COUNTERS
The W77IE58 has three 16-bit programmable timer/counters and one programmable Watchdog timer.
The Watchdog timer is operationally quite different from the other two timers.
Timer/Counters 0 & 1
The W77IE58 has two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit registers which
form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits register, and TL0,
the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The two can be
configured to operate either as timers, counting machine cycles or as counters counting external inputs.
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Publication Release Date: July 2000
Revision A1