W77IE58 Datasheet, PDF (56/90 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W77IE58
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts
are polled and their priority is resolved. If certain conditions are met then the hardware will execute an
internally generated LCALL instruction which will vector the process to the appropriate interrupt vector
address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt flag
is active in one cycle but not responded to, and is not active when the above conditions are met, the
denied interrupt will not be serviced. This means that active interrupts are not remembered; every polling
cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate service
routine. This may or may not clear the flag which caused the interrupt. In case of Timer interrupts, the
TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service
routine. In case of external interrupt, INT0 and INT1, the flags are cleared only if they are edge triggered.
In case of Serial interrupts, the flags are not cleared by hardware. In the case of Timer 2 interrupt, the
flags are not cleared by hardware. The Watchdog timer interrupt flag WDIF has to be cleared by
software. The hardware LCALL behaves exactly like the software LCALL instruction. This instruction
saves the Program Counter contents onto the Stack, but does not save the Program Status Word PSW.
The PC is reloaded with the vector address of that interrupt which caused the LCALL. These vector
address for the different sources are as follows
Table 8. Vector locations for interrupt sources
Source
Vector Address
Timer 0 Overflow
000Bh
Timer 1 Overflow
001Bh
Timer 2 Interrupt
002Bh
External Interrupt 2
0043h
External Interrupt 4
0053h
Watchdog Timer
0063h
Source
External Interrupt 0
External Interrupt 1
Serial Port
Serial Port 1
External Interrupt 3
External Interrupt 5
Vector Address
0003h
0013h
0023h
003Bh
004Bh
005Bh
The vector table is not evenly spaced; this is to accommodate future expansions to the device family.
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