W77IE58 Datasheet, PDF (58/90 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W77IE58
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to be
thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the register is
incremented on the falling edge of the external input pin, T0 in case of Timer 0, and T1 for Timer 1. The
T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one machine
cycle and low in the next, then a valid high to low transition on the pin is recognized and the count
register is incremented. Since it takes two machine cycles to recognize a negative transition on the pin,
the maximum rate at which counting will take place is 1/24 of the master clock frequency. In either the
"Timer" or "Counter" mode, the count register will be updated at C3. Therefore, in the "Timer" mode, the
recognized negative transition on pin T0 and T1 can cause the count register value to be updated only in
the machine cycle following the one in which the negative edge was detected.
The "Timer" or "Counter" function is selected by the "C / T " bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each
Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done by
bits M0 and M1 in the TMOD SFR.
Time-Base Selection
The W77IE58 gives the user two modes of operation for the timer. The timers can be programmed to
operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed. This will ensure
that timing loops on the W77IE58 and the standard 8051 can be matched. This is the default mode of
operation of the W77IE58 timers. The user also has the option to count in the turbo mode, where the
timers will increment at the rate of 1/4 clock speed. This will straight-away increase the counting speed
three times. This selection is done by the T0M and T1M bits in CKCON SFR. A reset sets these bits to
0, and the timers then operate in the standard 8051 mode. The user should set these bits to 1 if the
timers are to operate in turbo mode.
MODE 0
In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we
have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The
upper 3 bits of TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx moves
from 1 to 0, then the count in the THx register is incremented. When the count in THx moves from FFh
to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if TRx is set
and either GATE = 0 or INTx = 1. When C / T is set to 0, then it will count clock cycles, and if C / T
is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When
the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer overflow flag
TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when used as a timer,
the time-base may be either clock cycles/12 or clock cycles/4 as selected by the bits TxM of the
CKCON SFR.
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