W78ERD2 Datasheet, PDF (8/72 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2
6.3 Clock
The W78ERD2 is designed with either a crystal oscillator or an external clock.
6.4 Crystal Oscillator
The W78ERD2 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
6.5 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
6.6 Power Management
6.6.1 Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor
will exit idle mode when either an interrupt or a reset occurs.
6.6.2 Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
6.7 Reduce EMI Emission
If the crystal frequency is under 25 MHz, please option.b7 is set to 0 by the writer. Please refer option
bits description to operate this bit.
6.8 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78ERD2 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
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