W78ERD2 Datasheet, PDF (25/72 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2
F/W Flash Control
Bit:
7
0
6
5
WFWIN NOE
4
3
2
1
0
NCE CTRL3 CTRL2 CTRL1 CTRL0
Mnemonic: SFRCN Address: C7h
BIT
NAME
FUNCTION
7
-
Reserve
6
WFWIN On-chip Flash EPROM bank select for in-system programming.
0: 64K bytes Flash EPROM bank is selected as destination for re-
programming.
1: 4K bytes Flash EPROM bank is selected as destination for re-
programming.
5
OEN Flash EPROM output enable.
4
CEN Flash EPROM chip enable.
3~0 CTRL[3:0] The flash control signals
Timer 2 Control
Bit:
7
TF2
6
5
4
3
2
EXF2 RCLK TCLK EXEN2 TR2
Mnemonic: T2CON Address: C8h
1
0
C/T2 CP/RL2
BIT NAME
FUNCTION
7
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when
TF2
the count is equal to the capture register in down count mode. It can be set only
if RCLK and TCLK are both 0. It is cleared only by software. Software can also
set or clear this bit.
6
EXF2 Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2
underflow/overflow will cause this flag to set based on the CP/RL2, EXEN2 and
DCEN bits. If set by a negative transition, this flag must be cleared by software.
Setting this bit in software or detection of a negative transition on T2EX pin will
force a timer interrupt if enabled.
5
RCLK Receive clock Flag: This bit determines the serial port time-base when receiving
data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate
generation, else timer 2 overflow is used. Setting this bit forces timer 2 in baud
rate generator mode.
4
TCLK Transmit clock Flag: This bit determines the serial port time-base when
transmitting data in mode 1 and 3. If it is set to 0, the timer 1 overflow is used to
generate the baud rate clock, else timer 2 overflow is used. Setting this bit
forces timer 2 in baud rate generator mode.
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Publication Release Date: April 20, 2005
Revision A4