W78ERD2 Datasheet, PDF (36/72 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2
10. ENHANCED FULL DUPLEX SERIAL PORT
Serial port in the W78ERD2 is a full duplex port. The W78ERD2 provides the user with additional
features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports
are capable of synchronous as well as asynchronous communication. In Synchronous mode the
W78ERD2 generates the clock and operates in a half duplex mode. In the asynchronous mode, full
duplex operation is available. This means that it can simultaneously transmit and receive data. The
transmit register and the receive buffer are both addressed as SBUF Special Function Register.
However any write to SBUF will be to the transmit register, while a read from SBUF will be from the
receive buffer register. The serial port can operate in four different modes as described below.
10.1 MODE 0
This mode provides synchronous communication with external devices. In this mode serial data is
transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is
provided by the W78ERD2 whether the device is transmitting or receiving. This mode is therefore a
half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame.
The LSB is transmitted/received first. The baud rate is fixed at 1/12 of the oscillator frequency.
The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.
The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the
W78ERD2 and the device at the other end of the line. Any instruction that causes a write to SBUF will
start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all
8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling
edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high
again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on
TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures
that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift
clock on TxD or latched when the TxD clock is low.
osc
Write to
SBUF
Internal
Data Bus
PARIN SOUT
LOAD
CLOCK
RXD
P3.0 Alternate
Output Function
12
TX START TX SHIFT
Transmit Shift Register
TX CLOCK
TI
RI
REN
RXD
P3.0 Alternate
Iutput function
SERIAL
RI
CONTROLLE
RX
CLOCK
RX
START
SHIFT
CLOCK
LOAD SBUF
RX SHIFT
CLOCK
PAROUT
SIN
Serial Port Interrupt
TXD
P3.1 Alternate
Output function
SBUF
Read SBUF
SBUF
Internal
Data Bus
Receive Shift Register
Serial Port Mode 0
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