W78ERD2 Datasheet, PDF (48/72 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2
11.5 Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor. The watchdog timer function is only implemented in module4. However, module4 can
still be used for other modes if the watchdog is not needed. The user pre-loads a 16-bit value in the
compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer
value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST
pin to be high.
CIDL WDTE
-
-
-
CPS1 CPS0 ECF
CMOD(D9H)
Write To
CCAP4L
0
CCAP4H CCAP4L Module4
Write To
CCAP4H
16-bit Comparator
1
Enable
Match
CH
CL
PCA Timer/Counter
RESET
-
ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4
CCAPM4(DEH)
0
0
1
x
0
x
PCA Watchdog Timer Mode
12. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software
upset. The WDT consists of a 14-bit counter and the Watchdog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the
WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output reset HIGH pulse at the
RST-pin. It does not need the external pull-down resistor and pull-up CAP on the reset pin.
12.1 Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST
to avoid WDT overflow. The 14-bit counter overflows when it reaches 3FFFH and this will reset the
device. When WDT is enabled, it will increment every machine cycle while the oscillator is running.
This means the user must reset the WDT at least every 3FFFH machine cycles. To reset the WDT,
the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset
pin. To make the best use of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT reset. The RESET high pulse width
is 98 source clock at 12-clock mode, or 49 source clock at 6-clock mode.
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