W78ERD2 Datasheet, PDF (49/72 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2
13. DUAL DPTR
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a single
bit called DPS = AUXR1/bit0 that allows the program code to switch between them. The DPS bit status
should be saved by software when switching between DPTR0 and DPTR1. Note that bit 2 can’t be
written and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing
an INC DPTR instruction without affecting the GF2 bits.
14. IN-SYSTEM PROGRAMMING (ISP) MODE
The W78ERD2 equips one 64K byte of main Flash EPROM bank for application program (called AP
Flash EPROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LD Flash
EPROM). In the normal operation, the microcontroller executes the code in the AP Flash EPROM. If
the content of AP Flash EPROM needs to be modified, the W78ERD2 allows user to activate the In-
System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by
default, software must write two specific values 87H, then 59H sequentially to the CHPENR
register to enable the CHPCON write attribute. Writing CHPENR register with the values except
87H and 59H will close CHPCON register write attribute. The W78ERD2 achieves all in-system
programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in
the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a
wake-up from idle mode. Because device needs proper time to complete the ISP operations before
awaken from idle mode, software may use timer interrupt to control the duration for device wake-up
from idle mode. To perform ISP operation for revising contents of AP Flash EPROM, software located
at AP Flash EPROM setting the CHPCON register then enter idle mode, after awaken from idle mode
the device executes the corresponding interrupt service routine in LD Flash EPROM. Because the
device will clear the program counter while switching from AP Flash EPROM to LD Flash EPROM, the
first execution of RETI instruction in interrupt service routine will jump to 00H at LD Flash EPROM
area. The device offers software reset for switching back to AP Flash EPROM while the content of AP
Flash EPROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will
result a software reset to reset the CPU. The software reset serves as an external reset. This in-
system programming feature makes the job easy and efficient in which the application needs to
update firmware frequently. In some applications, the in-system programming feature make it possible
to easily update the system firmware without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming
mode. SFRFAH contains the high-order byte of address, SFRFAL contains the
low-order byte of address.
SFRFD: The programming data for on-chip Flash EPROM in programming mode.
SFRCN: The control byte of on-chip Flash EPROM programming mode.
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Publication Release Date: April 20, 2005
Revision A4