W19B320ATB Datasheet, PDF (8/53 Pages) Winbond – 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320AT/B
Accelerated Program Operation
The device provides accelerated program operations through the ACC function. This is one of two
functions provided by the #WP/ACC pin. This function is primarily intended to allow a faster
manufacturing throughput in the factory.
If #WP/ACC pin is set at V_HH, the device automatically enters into the Unlock Bypass mode. Then the
device will temporarily unprotect any protected sectors, and uses the higher voltage on this pin to
reduce the time required for program operations. The system would use a two-cycle program
command sequence required by the Unlock Bypass mode. When V_HH is removed from the #WP/ACC
pin, the device is back to a normal operation.
Please note that the #WP/ACC pin can not be at V_HH for operations except accelerated programming;
otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left floating;
otherwise, an unconnected inconsistent behavior will occur.
AUTOSELECT Functions
When the system writes the AUTOSELECT command sequence, the device enters the
AUTOSELECT mode. The system can then read AUTOSELECT codes from the internal register
(which is separate from the memory array) on DQ0 –DQ7. The standard read cycle timings are
applied in this mode. Please refer to the AUTOSELECT Mode and AUTOSELECT Command
Sequence sections for more information.
6.1.4 Simultaneous Read/Write Operations with Zero Latency
This device is capable of simultaneously reading data from one bank of memory and programming/
erasing in the other bank of memory. An erase operation may also be suspended to read from or
program to another location within the same bank (except the sector being erased).
6.1.5 Standby Mode
When the system is not reading or writing to the device, the device will be in a standby mode. In this
mode, current consumption is greatly reduced, and the outputs are in the high impedance state,
independent from the #OE input.
When the #CE and #RESET pins are both held at V_DD ± 0.3V, the device enters into the CMOS standby
mode (note that this is a more restricted voltage range than V_IH.) When #CE and #RESET are held at V_IH,
but not within V_DD ± 0.3V, the device will be in the standby mode, but the standby current will be greater.
The device requires standard access time (t_CE) for read access when the device is in either of these standby
modes, before it is ready to read data.
When the device is deselected during erasing or programming, the device initiates active current until
the operation is completed.
6.1.6 Automatic Sleep Mode
The automatic sleep mode minimizes device's energy consumption. When addresses remain stable
for t_ACC + 30ns, the device will enable this mode automatically. The automatic sleep mode is
independent from the #CE, #WE, and #OE control signals. Standard address access timings provide
new data when addresses are changed. In sleep mode, output data is latched and always available to
the system.
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