W19B320ATB Datasheet, PDF (14/53 Pages) Winbond – 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320AT/B
6.2.5 Unlock Bypass Command Sequence
The unlock bypass feature provides the system to program bytes or words to a bank which is faster
than using the standard program command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass
command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. In the same manner, additional data is programmed. This mode dispenses
with the initial two unlock cycles which required in the standard program command sequence,
resulting in faster total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence
to exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The
second cycle needs to contain the data 00h. Then, the bank returns to the read mode.
The device offers accelerated program operations by the #WP/ACC pin. When the V_HH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
V_HH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.6 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiate the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status
bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when that bank has returned to reading array data.
6.2.7 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiate the sector erase command
sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are
then followed by the address of the sector to be erased, and the sector erase command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations are not required in system.
A sector erase time-out of 50 μs occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
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