W19B320ATB Datasheet, PDF (37/53 Pages) Winbond – 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320AT/B
8.3 DC Characteristics
8.3.1 CMOS Compatible
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Input Load Current
ILI VIN =VSS to VDD, VDD = VDD (Max.)
-
-
±1.0 μA
A9 Input Load Current
ILIT VDD = VDD (Max.), A9 = 12.5V
-
-
35
μA
Output Leakage Current
ILO VOUT =VSS to VDD, VDD =VDD (Max.)
-
-
±1.0 μA
#CE = VIL, #OE = VIH 5 MHz
-
10
16
mA
VDD Active Read Current
(Note 1, 2)
Byte Mode
ICC1
#CE = VIL, #OE = VIH
1 MHz
5 MHz
2
4
mA
10
16
mA
Word Mode
1 MHz
2
4
mA
VDD Active Write Current
(Note 2, 3)
ICC2 #CE = VIL, #OE = VIH, #WE = VIL
-
15
30
mA
VDD Standby Current (Note2)
ICC3
#CE = VDD ±0.3V, #RESET = VDD
±0.3V
-
0.2
5
μA
VDD Reset Current (Note2)
ICC4 #RESET = VSS ±0.3V
-
0.2
5
μA
Automatic Sleep Mode
Current (note 2, 4)
ICC5 VIH = VDD ±0.3V, VIL = VSS ±0.3V
-
0.2
5
μA
VDD Active Read-While-
Program Current (note 1, 2)
ICC6 #CE = VIL, #OE = VIH
Byte
Word
-
21
45
mA
-
21
45
VDD Active Read-While-
Erase Current (note 1, 2)
ICC7 #CE = VIL, #OE = VIH
Byte
Word
-
21
45
mA
-
21
45
VDD Active Program-While-
Erase-Suspended Current ^{ICC8 #CE = VIL, #OE = VIH}
(note 2, 5)
-
17
35
mA
ACC Accelerated Program
Current, Word or Byte
IAcc #CE = VIL, #OE = VIH
ACC Pin
VDD Pin
5
10
mA
15
30
mA
Input Low Voltage
VIL
-
-0.5
-
0.8
V
Input High Voltage
VIH
-
0.7x VDD - VDD +0.3 V
Voltage for #WP/ACC Sector
Protect/ Unprotect and
Program Acceleration
VHH VDD =3.0V ±10%
8.5
-
9.5
V
Voltage for AUTOSELECT
and Temporary Sector
Unprotected
VID VDD =3.0V ±10%
8.5
-
12.5
V
Output Low Voltage
VOL IOL = 4.0 mA, VDD = VDD (Min.)
-
-
0.45
V
Output High Voltage
VOH1 IOH = -2.0 mA, VDD = VDD (Min.)
0.85 VDD -
-
V
VOH2 IOH = -100 μA, VDD = VDD (Min.)
VDD -0.4 -
-
Low VDD Lock-Out Voltage
VLKO
2.3
-
2.5
V
Notes:
1. The I_CC current listed is typically less than 2 mA/ MHz, with #OE at V_IH.
2. Maximum I_CC specifications are tested with V_DD = V_DD max.
3. I_CC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC + 30 ns. Typical sleep mode
current is200 nA.
- 37 -
Publication Release Date: December 27, 2005
Revision A4