W19B320ATB Datasheet, PDF (11/53 Pages) Winbond – 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320AT/B
In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest
addressable memory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in
byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the highest
8 Kbytes boot sector at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h–
3FE00Fh in byte mode). Customers may choose have their code programmed by Winbond. Winbond
can program the customer’s code, with or without the random ESN. The devices are then shipped with
the Security Sector permanently locked.
Customer Lockable: Security Sector NOT Programmed or Protected At the Factory
If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory
space. When in system design, this issue should be considered. The Security Sector can be read,
programmed; but cannot be erased. Please note that when programming the Security Sector, the
accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector
area can be protected using one of the following procedures:
• Write the three-cycle Enter Security Sector Region command sequence, and then follow the
in-system sector protect algorithm, except that #RESET may be at either V IH or VID. This
allows in-system protection of the Security Sector without raising any device pin to a high
voltage.
Please note that this method is only suitable for the Security Sector.
• To verify the protect/unprotect status of the Security Sector; follow the algorithm show in
Security Sector Protect Verify.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotect the Security Sector area and none of the bits in the Security Sector memory space can be
modified in any ways.
6.1.14 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during V_DD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = V_IL, #CE = V_IH or #WE = V_IH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = V_IL and #OE = V_IH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
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Publication Release Date: December 27, 2005
Revision A4