W19B320ATB Datasheet, PDF (41/53 Pages) Winbond – 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320AT/B
8.10 Alternate #CE Controlled Erase and Program Operations
PARAMETER
SYM.
MIN.
70 NS
TYPICAL
(NOTE3)
MAX.
(NOTE4)
UNIT
Write Cycle Time (Note 1)
TWC
70
-
-
ns
Address Setup Time
TAS
0
-
-
ns
Address Hold Time
TAH
45
-
-
ns
Data Setup Time
TDS
35
-
-
ns
Data Hold Time
TDH
0
-
-
ns
Read Recover Time Before Write (#OE High
to #WE Low)
TGHEL
0
-
-
ns
#WE Setup Time
TWS
0
-
-
ns
#WE Hold Time
TWH
0
-
-
ns
#CE Pulse Width
TCP
30
-
-
ns
#CE Pulse Width High
TCPH
30
-
-
ns
Byte
TPB
-
Programming Time (Note 6)
Word
TPW
-
5
150
μs
7
210
Accelerated Programming
Time (Note 6)
Byte
TACCP
-
Word
4
120
μs
Sector Erase Time (Note 2)
TSE
-
0.4
15
sec
Chip Erase Time (Note 2)
TCE
-
49
-
sec
Byte
TCPB
-
21
63
Chip Program Time (Note 5)
sec
Word
TCPW
-
14
42
Notes:
1. Not 100 % tested.
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 100,000 cycles .Additionally,
programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90℃, VDD =2.7V, 100,000 cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most
bytes program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 100,000 cycles.
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Publication Release Date: December 27, 2005
Revision A4