ISD5116 Datasheet, PDF (8/57 Pages) Winbond – Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability

2.1 INTERNAL REGISTERS
The ISD5116 has multiple internal registers that are used to store the address information and the
configuration or set-up of the device. The two 16-bit configuration registers control the audio paths
through the device, the sample frequency, the various gains and attenuations, the sections powered up
and down, and the volume settings. These registers are discussed in detail in section 3.5 on page 13.
2.2 MEMORY ORGANIZATION
The ISD5116 memory array is arranged as 2048 rows (or pages) of 2048 bits for a total memory of
4,194,304 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the
analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus at 8 kHz
there is actually room for 8 minutes and 44 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The
contents of a page are either analog or digital. This is determined by instruction (op code) at the time the
data is written. A record of what is analog and what is digital, and where, is stored by the system
microcontroller in the message address table (MAT). The MAT is a table kept in the microcontroller
memory that defines the status of each message “block.” It can be stored back into the ISD5116 if the
power fails or the system is turned off. Using this table allows for efficient message management.
Segments of messages can be stored wherever there is available space in the memory array. [This is
explained in detail for the ISD5008 in Applications Note #9 and will be similarly described in a later Note
for the ISD5116.]
When a page is used for analog storage, the same 32 blocks are present but there are 8 EOM (End-of-
Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus, when
recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when the
Stop command is given, but continues until the 32 millisecond block is filled. Then a bit is placed in the
EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode.
Digital data is sent and received serially over the I²C interface. The data is serial-to-parallel converted and
stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it
becomes the register that is parallel written into the array. The prior write register becomes the new serial
input register. A mechanism is built-in to ensure there is always a register available for storing new data.
Storing data in the memory is accomplished by accepting data one byte at a time and issuing an
acknowledge. If data is coming in faster than it can be written, the chip issues an acknowledge to the host
microcontroller, but holds SCL LOW until it is ready to accept more data.
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
array and serially sent to the I²C interface. (See section 5 on page 27 for details).
October 2000
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