ISD5116 Datasheet, PDF (31/57 Pages) Winbond – Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability

3. Erase digital data
1. Host executes I²C START
2. Send Slave Address with R/W bit = “0” (Write)
3. Slave responds back with an ACK
4. Wait for SCL to go HIGH
5. Host sends a byte to Slave - (Command Byte = D1)
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK.
10. Wait for SCL to go HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL to go HIGH
14. Host executes I²C STOP
15. Host counts RAC cycles to track where the chip is in the erase operation.
16. Host determines erase of final row has begun
17. Host executes I²C START
18. Send Slave Address with R/W bit = “0” (Write)
19. Slave responds back with an ACK
20. Wait for SCL to go HIGH
21. Host sends a byte to Slave - (Command Byte = 80)
22. Slave responds back with an ACK
23. Wait for SCL to go HIGH
24. Host executes I²C STOP
Erase starts on falling
edge of Slave
acknowledge
S SLAVE ADDRESS W A D1h A DATA A DATA A P Note 2
Command Byte _{High Addr. Byte} Low Addr. Byte
"N" RAC cycles Last erased row S SLAVE ADDRESS W A ^80h
Note 3.
Note 4.
AP
Notes
1.
Command Byte
Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low
Address Byte will be ignored.
2. I2C bus is released while erase proceeds. Other devices may use the bus until it is
time to execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end
of each erased row. The erase of the "next" row begins with the rising edge of RAC.
See the Digital Erase RAC timing diagram on page 32.
4. When the erase of the last desired row begins, the following STOP command
(Command Byte = 80 hex) must be issued. This command must be completely given,
including receiving the ACK from the Slave before the RAC pin goes HIGH .25
microseconds before the end of the row.
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