ISD5116 Datasheet, PDF (18/57 Pages) Winbond – Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability

1.
Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
2.
Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
3.
Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM1
mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down
these two amplifiers.
4.
Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage in
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
5.
Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
6.
Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0,
bit D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and
D12 respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and
FLD1 are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band
pass setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and
S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and
VOL2 are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control.
(g). Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two
registers must be loaded in this order. The internal set up for both registers will take effect synchronously
with the rising edge of SCL.
3.8 CALL RECORD
The call record mode adds the ability to record an incoming phone call. In most applications, the
ISD5116 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5116 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE FILTER
MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed Through
Mode has already powered up the ANA IN amp so we only need to power up and enable the path to the
Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the state
where both D9 and D10 are ZERO to select the ANA IN path.
October 2000
Page 17