ISD5116 Datasheet, PDF (20/57 Pages) Winbond – Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability

5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
3.10 MEMO AND CALL PLAYBACK
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From
there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo
speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered
down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the state
of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL
STORAGE ARRAY.
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They
should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING
amplifier.
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to
power-up the VOLUME CONTROL.
7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1, and VOL2 control the state of the VOL-
UME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary
count of 000 through 111 controls the amount of attenuation through that state. In most cases,
the software will select an attenuation level according to the desires of the current users of the
October 2000
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