ISD5116 Datasheet, PDF (50/57 Pages) Winbond – Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability

9.2 I²C Protocol
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that
indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being
sent from the current bus master to the device being addressed. This single bit is a 0 for a Read cycle,
which indicates that the data is being sent from the device being addressed to the current bus master. For
example, the valid Slave Addresses for the ISD5116 device, for both Write and Read cycles, are shown in
Section 3.1.1 on page 9 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1^st byte following the Start
Condition sequence. An example of a Master transmitting an address to a ISD5116 slave is shown below.
In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write cycle. All the bits
transferred are from the Master to the Slave, except for the indicated Acknowledge bits. The following
example details the transfer explained in Section 3.1.2-3 on page 10 of this datasheet.
Master Transmits to Slave Receiver (Write) Mode
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S SLAVE ADDRESS W A
COMMAND BYTE
A
High ADDR. BYTE
A
Low ADDR. BYTE
AP
Start Bit
R/W
Stop Bit
A common procedure in the ISD5116 is the reading of the Status Bytes. The Read Status condition in the
ISD5116 is triggered when the Master addresses the chip with its proper Slave Address, immediately
followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an example of the
Master sending to the Slave, immediately followed by the Slave sending data back to the Master. The “N”
not-acknowledge cycle from the Master ends the transfer of data from the Slave. The following example
details the transfer explained in Section 3.1.2-1 on page 9 of this datasheet.
Master Reads from Slave immediately after first byte (Read Mode)
a cknow le dge m e nt
from sla ve
F rom S la ve
F rom S la ve
F rom S la ve
S
SLAVE ADDRESS R A
F rom M aster
S ta rt Bit
F rom
M aste r
R/W
F rom
M aste r
STATUS W ORD
A
High ADDR. BYTE
A
Low ADDR BYTE
NP
a cknow le dge m e nt
from M aste r
a cknow le dge m e nt
from M aste r
S top Bit
F rom
M aste r
not-a cknowle dge d
from M aste r
Another common operation in the ISD5116 is the reading of digital data from the chip’s memory array at a
specific address. This requires the I²C interface Master to first send an address to the ISD5116 Slave
device, and then receive data from the Slave in a single I²C operation. To accomplish this, the data
direction R/W bit must be changed in the middle of the command. The following example shows the
Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the
ISD5116, and then immediately changing the data direction and reading some number of bytes from the
chip’s digital array. An unlimited number of bytes can be read in this operation. The “N” not-acknowledge
October 2000
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