W25Q64FV_13 Datasheet, PDF (76/89 Pages) Winbond – 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q64FV
AC Electrical Characteristics (cont’d)
DESCRIPTION
SPEC
SYMBOL ALT
UNIT
MIN TYP MAX
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX⁽²⁾ tLZ
7
ns
/HOLD to Output High-Z
tHLQZ⁽²⁾
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL⁽³⁾
20
ns
Write Protect Hold Time After /CS High
tSHWL⁽³⁾
100
ns
/CS High to Power-down Mode
tDP⁽²⁾
3
µs
/CS High to Standby Mode without Electronic Signature
Read
tRES1⁽²⁾
3
µs
/CS High to Standby Mode with Electronic Signature
Read
tRES2⁽²⁾
3
µs
/CS High to next Instruction after Suspend
tSUS⁽²⁾
20
µs
/CS High to next Instruction after Reset
tRST⁽²⁾
30
µs
Write Status Register Time
tW
15
20 ms
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
Page Program Time
t_BP1(4)
t_BP2(4)
tPP
20
50
µs
2.5
10
µs
0.7
3
ms
W25Q64FVxxIG
Sector Erase Time (4KB)
W25Q64FVxxIQ &
tSE
W25Q64FVxxIF
60
400 ms
45
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
tBE₁
120 1,600 ms
tBE₂
150 2,000 ms
tCE
20
100
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4. For multiple bytes after first byte within a page, t_BPN = t_{BP1 +} t_{BP2 * N} (typical) and t_BPN = t_{BP1 +} t_{BP2 * N} (max), where N = number
of bytes programmed.
5. 4-bytes address alignment for QPI/Quad Read
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