W25Q64FV_13 Datasheet, PDF (28/89 Pages) Winbond – 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q64FV
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to
enter and operate in the QPI mode.
Please refer to 7.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits
are 0.
/CS
CLK
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 3
Mode 0
DI
(IO₀)
DO
(IO₁)
* ^{= MSB}
Instruction (01h)
Status Register 1 in
Status Register 2 in
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
*
*
High Impedance
Figure 9a. Write Status Register Instruction (SPI Mode)
/CS
CLK
IO₀
Mode 3
Mode 0
012345
Instruction
01h
SR1 in
40
SR2 in
12 8
Mode 3
Mode 0
IO₁
5 1 13 9
IO₂
6 2 14 10
IO₃
7 3 15 11
Figure 9b. Write Status Register Instruction (QPI Mode)
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