W989D6DB Datasheet, PDF (7/64 Pages) Winbond – Standard Self Refresh Mode

W989D6DB / W989D2DB
5. BALL DESCRIPTION
5.1 Signal Description
Ball Name
A [n:0]
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
CS
RAS
CAS
Function
Description
Address
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
Multiplexed pins for data output and input.
Data Input/ Output
Chip Select
Row Address
Strobe
Column Address
Strobe
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
Command input. When sampled at the rising edge of the
clock, RAS , CAS and WE define the operation to be
executed.
Referred to RAS
WE
Write Enable _{Referred to WE}
UDQM / LDQM(x16)
DQM0~DQM3 (x32)
I/O Mask
The output buffer is placed at Hi-Z (with latency of 2 in
CL=2, 3;) when DQM is sampled high in read cycle. In
write cycle, sampling DQM high will block the write
operation with zero latency
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode or Self
Refresh mode is entered.
VDD
Power
Power supply for input buffers and logic circuit inside
DRAM.
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
VDDQ
Power for I/O Buffer
Power supply separated from VDD, used for output
buffers to improve noise.
VSSQ
Ground for I/O Separated ground from VSS, used for output buffers to
Buffer
improve noise.
NC
No Connection No connection
Publication Release Date: Mar. 19, 2014
-7-
Revision: A01-001