W989D6DB Datasheet, PDF (17/64 Pages) Winbond – Standard Self Refresh Mode

W989D6DB / W989D2DB
7.1.18 Self Refresh Exit Command
(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)
This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any
subsequent command from the end of the Self Refresh Exit command.
7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command
(CKE = L)
The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The
device state is held intact while the CLK is suspended. On the other hand, when the device is not operating the
Burst cycle, this command performs entry into Power Down mode. All input and output buffers (except the CKE
buffer) are turned off in Power Down mode.
7.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command
(CKE = H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command
(asserting CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled
buffers are turned on to the active state. Any subsequent commands can be issued after one clock cycle from the
end of this command.
7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command
(DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H)
During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals
control the input buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0-3 signals control of
the output buffers per byte.
I/O Org.
× 16
× 32
Mask Pin
LDQM
UDQM
DQM0
DQM1
DQM2
DQM3
Masked DQs
DQ0~DQ7
DQ8~DQ15
DQ0~DQ7
DQ8~DQ15
DQ16~DQ23
DQ24~DQ31
8. OPERATION
8.1 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is
issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized to the positive
edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency from the
issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the
burst length of read data and Addressing Mode must be set. Each bank is held in the active state unless the
Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other
commands. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of
the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending
tRCD.
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is
terminated.
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or
Precharge command is issued.
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Publication Release Date: Mar. 19, 2014
Revision: A01-001