W989D6DB Datasheet, PDF (22/64 Pages) Winbond – Standard Self Refresh Mode

W989D6DB / W989D2DB
8.5 Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three
fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate the
column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The
data to be set in the Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of
the Mode Register after power-up is undefined; therefore the Mode Register Set command must be issued before
proper operation.
8.5.1 Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2,
4, 8, words, or full-page.
A2
A1
A0
Bust Length
0
0
0
1 word
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
1
1
Full-Page
8.5.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0,
Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support
burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports the full-page burst.
A3
Addressing Mode
0
Sequential
1
Interleave
8.5.3 Addressing Sequence for Sequential Mode
A column access is performed by incrementing the column address input to the device. The address is varied by
the Burst Length shown as below table.
DATA
Access Address
Burst Length
Data 0
n
2 words (Address bit is A0)
Data 1
Data 2
Data 3
Data 4
n+1
n+2
n+3
n+4
not carried from A0 to A1
4 words (Address bit is A1, A0)
not carried from A1 to A2
Data 5
Data 6
n+5
n+6
8 words (Address bit is A2, A1, A0)
not carried from A2 to A3
Data 7
n+7
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Publication Release Date: Mar. 19, 2014
Revision: A01-001