W989D6DB Datasheet, PDF (30/64 Pages) Winbond – Standard Self Refresh Mode

W989D6DB / W989D2DB
9.6.2 AC Test Condition
Symbol
VIH(min)
VIL(max)
VOTR
Parameter
Input High Voltage Level (AC)
Input Low Voltage Level (AC)
Output Signal Reference Level
Value
0.8 x VDDQ
0.2 x VDDQ
0.5 x VDDQ
Unit
V
V
V
I/O
Z₀ = 50 Ohms
Time Reference Load
20pF
Input signal transition time between VIH and VIL is assumed as 1 Volts/nS.
Notes:
1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent
damage to the device. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended
periods may affect deice reliability.
2. All voltages are referenced to VSS and VSSQ.
3. These parameters depend on the cycle rate. These values are measured at a cycle rate with the
minimum values of tCK and tRC . Input signals transition once per tCK period.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in note 9.
6. AC Test Conditions: (refer to 9.6.2).
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output voltage levels.
8. These parameters account for the number of clock cycles and depend on the operating frequency of
the clock, as follows: The number of clock cycles = specified value of timing / clock period (count
fractions as a whole number).
9. Power up Sequence: The SDRAM should be powered up by the following sequence of operations.
a. Power must be applied to VDD before or at the same time as VDDQ while all input signals are
held in the “NOP” state. The CLK signal will be applied at power up with power.
b. After power-up a pause of at least 200 μS is required. It is required that DQM and CKE signals
must be held “High” (VDD levels ) to ensure that the DQ output is in High-impedance state.
c. All banks must be precharged.
d. The Mode Register Set command must be issued to initialize the Mode Register.
e. The Extended Mode Register Set command must be issued to initialize the Extended Mode
Register.
f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
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Publication Release Date: Mar. 19, 2014
Revision: A01-001