W989D6DB Datasheet, PDF (21/64 Pages) Winbond – Standard Self Refresh Mode

W989D6DB / W989D2DB
8.4 Burst Termination
The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted
by a Write command, the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation
is to be interrupted by a Read command, only the input data before the Read command is enable and the input
data after the Read command is disabled.
- Read Interrupted by a Precharge
A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is
interrupted by a Precharge command, the read operation is terminated after (CAS latency-1) clock cycles
from the Precharge command.
- Write Interrupted by a Precharge
A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock
cycle at which the Precharge command is issued. In this case, the DQM signal must be asserted high to
prevent writing the invalid data to the cell array.
- Read Interrupted by a Burst Stop
When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated.
When the Burst Stop command is issued during a Burst Read cycle, the read operation is terminated after
clock cycle of (CAS latency-1) from the Burst Stop command.
- Write Interrupted by a Burst Stop
When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the
same clock cycle that the Burst Stop command is issued.
- Write Interrupted by a Read
A burst of write operation can be interrupted by a read command. The read command interrupts the write
operation on the same clock that the read command is issued. All the burst writes that are presented on the
data bus before the read command is issued will be written to the memory. Any remaining burst writes will
be ignored once the read command is activated. There must be at least one clock bubble (Hi-Z state) on the
data bus to avoid bus contention.
- Read Interrupted by a Write
A burst of read operation can be interrupted by a write command by driving output drivers in a Hi-Z state using
DQM before write to avoid data conflict. DQM should be utilized if there is data from a Read command on the first
and second cycles of the subsequent write cycles to ensure the read data are tri-stated. From the third clock
cycle, the write command will control the data bus and DQM is not needed.
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Publication Release Date: Mar. 19, 2014
Revision: A01-001