W949D6DB Datasheet, PDF (7/60 Pages) Winbond – Standard Self Refresh Mode

W949D6DB / W949D2DB
5. BALL DESCRIPTION
5.1 Signal Descriptions
SIGNAL NAME
A [n:0]
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
TYPE
Input
Input
I/O
FUNCTION
Address
Bank Select
Data Input/
Output
DESCRIPTION
Provide the row address for ACTIVE commands, and
the column address and AUTO PRECHARGE bit for
READ/WRITE commands, to select one location out of
the memory array in the respective bank. The address
inputs also provide the opcode during a MODE
REGISTER SET command.
A10 is used for Auto Pre-charge Select.
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data bus: Input / Output.
CS enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are
CS
Input Chip Select _{masked when CS is registered HIGH. CS provides}
for external bank selection on systems with multiple
banks. CS is considered part of the command code.
RAS
CAS
Input
Input
Row Address
Strobe
Column
Address
Strobe
RAS , CAS and WE (along with CS ) define the
command being entered.
Referred to RAS _.
WE
UDM, LDM (x16);
DM0 to DM3 (x32)
Input
Input
Write Enable
Input Mask
Referred to RAS _.
Input Data Mask: DM is an input mask signal for write
data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM pins are
input-only, the DM loading matches the DQ and DQS
loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15,
DM2: DQ16 – DQ23, DM3: DQ24 – DQ31.
CK / CK
Input
Clock Inputs
CK and CK are differential clock inputs. All address
and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK .Input
and output data is referenced to the crossing of CK and
CK (both directions of crossing). Internal clock signals
are derived from CK/ CK .
Publication Release Date: Oct. 08, 2014
Revision: A01-003
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