W949D6DB Datasheet, PDF (14/60 Pages) Winbond – Standard Self Refresh Mode

W949D6DB / W949D2DB
7.3 Mode Register Definition
BA1 BA0
An...A7 (see Note 1)
A6 A5 A4 A3 A2 A1 A0 Address Bus
00
0 (see Note 2)
CAS Latency BT Burst Length Mode Register
A6 A5 A4 CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A2 A1 A0 Burst Length
000
Reserved
001
2
010
4
011
8
100
16
101
Reserved
110
Reserved
111
Reserved
NOTE:
1.MSB depends on LPDDR SDRAM density.
2.Alogic 0 should be programmed to all unused / undefined address bits to future compatibility.
7.3.1 Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length and burst type
being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential
and the interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within the block, meaning that the burst will wrap within
the block if a boundary is reached.
The block is uniquely selected by A1−An when the burst length is set to two, by A2−An when the burst
length is set to 4, by A3−An when the burst length is set to 8 (where An is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. The programmed burst length applies to both read and write
bursts.
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Publication Release Date: Oct. 08, 2014
Revision: A01-003