W949D6DB Datasheet, PDF (55/60 Pages) Winbond – Standard Self Refresh Mode

W949D6DB / W949D2DB
PARAMETER
SYM.
-5
-6
UNIT NOTES
MIN. MAX. MIN. MAX.
ACTIVE to ACTIVE command period
tRC
tRAS +
tRP
tRAS +
tRP
nS
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
tRFC
72
72
nS
ACTIVE to READ or WRITE delay
tRCD
15
18
nS
PRECHARGE command period
tRP
3
3
tCK
ACTIVE bank A to ACTIVE bank B delay
tRRD
10
12
nS
WRITE recovery time
tWR
15
15
nS
24
Auto precharge write recovery + precharge time
tDAL
-
-
tCK
25
Internal write to Read command delay
tWTR
1
1
tCK
Self Refresh exit to next valid command delay
tXSR
120
120
nS
26
Exit power down to next valid command delay
tXP
2
1
tCK
27
CKE min. pulse width (high and low pulse width)
tCKE
1
1
tCK
Refresh Period
tREF
64
64
mS
Average periodic refresh interval
tREFI
7.8
7.8
μS
28,29
MRS for SRR to READ
tSRR
2
2
tCK
READ of SRR to next valid command
tSRC
CL+1
CL+1
tCK
Notes:
1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device operation
are guaranteed for the full voltage and temperature range specified.
4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission
line terminated at the tester electronics). For the half strength driver with a nominal 10pF load parameters tAC and tQH are
expected to be in the same range. However, these parameters are not subject to production test but are estimated by design
/ characterization. Use of IBIS or other simulation tools for system design validation is suggested.
Full Drive Strength
I/O
Z₀ = 50 Ohms
20 pF
Half Drive Strength
I/O
Z₀ = 50 Ohms
10 pF
Time Reference Load
5. The CK/ CK input reference voltage level (for timing referenced to CK/ CK ) is the point at which CK and CK cross; the
input reference voltage level for signals other than CK/ CK is VDDQ/2.
6. The timing reference voltage level is VDDQ/2.
7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating
conditions.
8. A CK/ CK differential slew rate of 2.0 V/nS is assumed for all parameters.
9. CAS Latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ command
was registered; with CL = 2 the first data element is valid at (tCK + tAC) after the clock at which the READ command was
registered.
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits of tCL and tCH)
- 55 -
Publication Release Date: Oct. 08, 2014
Revision: A01-003