W949D6DB Datasheet, PDF (11/60 Pages) Winbond – Standard Self Refresh Mode

W949D6DB / W949D2DB
7. FUNCTIONAL DESCRIPTION
7.1 Initialization
LPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures
other than those specified may result in undefined operation. If there is any interruption to the device
power, the initialization routine should be followed. The steps to be followed for device initialization are
listed below.
The Mode Register and Extended Mode Register do not have default values. If they are not programmed
during the initialization sequence, it may lead to unspecified operation. The clock stop feature is not
available until the device has been properly initialized from Step 1 through 11.
 Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be
brought up simultaneously to prevent device latch-up. Although not required, it is
recommended that VDD and VDDQ are from the same power source. Also assert and hold
Clock Enable (CKE) to a LVCMOS logic high level.
 Step 2: Once the system has established consistent device power and CKE is driven high, it is safe
to apply stable clock.
 Step 3: There must be at least 200μS of valid clocks before any command may be given to the DRAM.
During this time NOP or DESELECT commands must be issued on the command bus.
 Step 4: Issue a PRECHARGE ALL command.
 Step 5: Provide NOPs or DESELECT commands for at least tRP time.
 Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least
tRFC time. Issue the second AUTO REFRESH command followed by NOPs or DESELECT
command for at least tRFC time. Note as part of the initialization sequence there must be two
Auto Refresh commands issued. The typical flow is to issue them at Step 6, but they may
also be issued between steps 10 and 11.
 Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.
 Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
 Step 9: Using the MRS command, program the extended mode register for the desired operating
modes. Note the order of the base and extended mode register programmed is not important.
 Step 10: Provide NOP or DESELECT commands for at least tMRD time.
 Step 11: The DRAM has been properly initialized and is ready for any valid command.
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Publication Release Date: Oct. 08, 2014
Revision: A01-003